Welcome to our live workshop in person!
We were happy to meet again with industry leaders, showcasing our latest solutions to the High-Speed Design workflow.
The latest technology for high speed SerDes and memory interfaces is now getting into the multi-gigabit range where there is less design margin given to design engineer. As a result creating a stable and compliant design is more challenging than ever before and standard analysis is no longer sufficient.
Our Keysight experts will showcase comprehensive workflow for the latest memory standards, integrated analysis for DDR memory designs, faster simulations.
Agenda
| Time: | Topic | Speaker |
| 9:00 - 9:30 | Welcome Tea Break | |
| 9:30 -10:30 | What's New and Memory and SerDes Great Demo | Hee-Soo Lee |
| 10:30 - 11:20 | Generating AMI Models for SerDes Applications | Hee-Soo Lee |
| 11:20 - 12:10 | How to Efficiently Build and Analyze Memory Bus to Meet DDR Specification | Hee-Soo Lee |
| 12:10 - 12:20. | Lucky draw winner's announcment |
Register now to learn from Keysight experts, and stand a chance to win home great prizes.
